Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET-Reference-Cited by-同舟云学术

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Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET

Published:2024-05 Issue:5 Volume:71 Page:2950-2956
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Nirala Rohit Kumar¹^ORCID,Semwal Sandeep¹,Gupta Manish²^ORCID,Kranti Abhinav¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Low Power Nanoelectronics Research Group, Central Workshop Building, Indian Institute of Technology Indore, Indore, Madhya Pradesh, India

2. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science (BITS) Pilani, Zuarinagar, Goa, India

Funder

Science and Engineering Research Board (SERB), Department of Science and Technology (DST), Government of India

Junior Research Fellowship Award, University Grants Commission, Ministry of Education, Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10508280/10464250.pdf?arnumber=10464250

Reference44 articles.

1. Future of dynamic random-access memory as main memory

2. Improving energy efficiency of embedded DRAM caches for high-end computing systems

3. A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

4. Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

5. Monolithic 3D integration advances and challenges: From technology to system levels

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