Author:
Chuang Chin-Lung,Cheng Wei-Hsiang,Lu Dong-Jung,Liu Chien-Nan Jimmy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
9 articles.
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1. REMU: Enabling Cost-Effective Checkpointing and Deterministic Replay in FPGA-based Emulation;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06
2. A novel FPGA-based test-bench framework for SDI stream verification;EURASIP Journal on Image and Video Processing;2020-07-16
3. DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles;2018 28th International Conference on Field Programmable Logic and Applications (FPL);2018-08
4. A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017
5. Cost Effective Partial Scan for Hardware Emulation;2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2016-05