Chip scale package (CSP) solder joint reliability and modeling
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx4/5459/14724/00670560.pdf?arnumber=670560
Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-01
2. DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package;IEEE Access;2021
3. Failure mechanism of lead-free component boards in thermomechanical test based on recrystallization enhanced cracking;Microelectronics Reliability;2020-07
4. Effects of package geometry on thermal fatigue life and microstructure of Sn–Ag–Cu solder joint;Materials Science and Technology;2011-11
5. A Probabilistic Approach to Predict Thermal Fatigue Life for Ball Grid Array Solder Joints;Journal of Electronic Materials;2011-09-09
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