Panel-Level Chip-Scale Package With Multiple Diced Wafers-Reference-Cited by-同舟云学术

Panel-Level Chip-Scale Package With Multiple Diced Wafers

Published:2020-07 Issue:7 Volume:10 Page:1110-1124
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Lau John H.^ORCID,Ko Cheng-Ta,Tseng Tzyy-Jang,Yang Kai-Ming,Peng Tony Chia-Yu,Xia Tim,Lin Puru Bruce,Lin Eagle^ORCID,Chang Leo,Liu Hsing Ning,Cheng David

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/9139415/09099305.pdf?arnumber=9099305

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