Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers-Reference-Cited by-同舟云学术

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

Published:2018-10 Issue:10 Volume:8 Page:1729-1737
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Lau John H.^ORCID,Li Ming,Yang Lei,Li Margie,Xu Iris,Chen Tony,Chen Sandy,Yong Qing Xiang,Madhukumar Janardhanan Pillai^ORCID,Kai Wu,Fan Nelson,Kuah Eric,Li Zhang,Tan Kim Hwee,Bao Winsons,Lim Sze Pei,Beica Rozalia,Ko Cheng-Ta,Xi Cao

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/8488701/08410017.pdf?arnumber=8410017

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