Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling-Reference-Cited by-同舟云学术

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Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling

Published:2009-04 Issue:4 Volume:56 Page:773-783
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

An Hu ,Fei Yuan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/4813280/04588356.pdf?arnumber=4588356

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation;IEEE Transactions on Circuits and Systems II: Express Briefs;2020-10

2. An area-efficient and wide-range digital DLL for per-pin deskew applications;TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES;2017

3. Minimum jitter‐based adaptive decision feedback equaliser for giga‐bit‐per‐second serial links;The Journal of Engineering;2015-01

4. New 2-D Eye-Opening Monitor for Gb/s Serial Links;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-06

5. Design techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review;IET Circuits, Devices & Systems;2014-03

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