Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8919/4516005/04436077.pdf?arnumber=4436077
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity;IEEE Transactions on Signal and Power Integrity;2022
2. A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver;Electronics;2021-08-03
3. Root Cause Analysis for the Phase Noise of the Clock Generator;2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium;2021-07-26
4. Clock System Architecture for Digital Circuits;International Conference on Intelligent Computing and Smart Communication 2019;2019-12-20
5. Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-12
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