A low-cost serial decoder architecture for low-density parity-check convolutional codes-Reference-Cited by-同舟云学术

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A low-cost serial decoder architecture for low-density parity-check convolutional codes

Published:2008-08 Issue:7 Volume:55 Page:1967-1976
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Bates S.,Zhengang Chen ,Gunthorpe L.,Pusane A.E.,Zigangirov K.Sh.,Costello Daniel J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8919/4599140/04447002.pdf?arnumber=4447002

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An FPGA-Based LDPC Decoder With Ultra-Long Codes for Continuous-Variable Quantum Key Distribution;IEEE Access;2021

2. LDPC decoder architectures;Resource Efficient LDPC Decoders;2018

3. Performance Comparison of LDPC Block and Spatially Coupled Codes Over GF $(q)$;IEEE Transactions on Communications;2015-03

4. Implementation of Decoders for LDPC Block Codes and LDPC Convolutional Codes Based on GPUs;IEEE Transactions on Parallel and Distributed Systems;2014-03

5. A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes;IEEE Transactions on Circuits and Systems I: Regular Papers;2013-07

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