Author:
Sawada K.,Sakurai T.,Nogami K.,Shirotori T.,Takayanagi T.,Iizuka T.,Maeda T.,Matsunaga J.,Fuji H.,Maeguchi K.,Kobayashi K.,Ando T.,Hayakashi Y.,Miyoshi A.,Sato K.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
6 articles.
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2. Consolidated conflict detection for hardware transactional memory;Proceedings of the 23rd international conference on Parallel architectures and compilation;2014-08-24
3. Efficient fault tolerant cache memory design;Microprocessing and Microprogramming;1995-05
4. A 110-MHz/1-Mb synchronous TagRAM;IEEE Journal of Solid-State Circuits;1994-04
5. An analytical access time model for on-chip cache memories;IEEE Journal of Solid-State Circuits;1992