gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation
Author:
Affiliation:
1. INESC-ID, Instituto Superior Técnico, University of Lisbon, Lisboa, Portugal
2. Instituto de Telecomunicações, University of Coimbra, Coimbra, Portugal
Funder
national funds through Funda****ão para a Ci****ncia e a Tecnologia
European High Performance Computing Joint Undertaking (JU) under Framework Partnership
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/10208/10375809/10304264.pdf?arnumber=10304264
Reference13 articles.
1. Design Space Exploration for Distributed Cyber-Physical Systems: State-of-the-art, Challenges, and Directions
2. Analytic Multi-Core Processor Model for Fast Design-Space Exploration
3. NAPEL
4. The gem5 simulator
5. gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM
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