gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM
Author:
Affiliation:
1. INESC-ID, Instituto Superior Técnico, University of Lisbon,Portugal
2. Instituto de Telecomunicações, University of Coimbra,Portugal
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980889/9980894/09980925.pdf?arnumber=9980925
Reference29 articles.
1. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars;shafiee;ISCA,2016
2. MAGIC—Memristor-Aided Logic
3. Accelerating inference on binary neural networks with digital RRAM processing;vieira;VLSI-SoC (Selected Papers),2019
4. RRAM variability and its mitigation schemes
5. Exploiting Compute Caches for Memory Bound Vector Operations
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM;IEEE Access;2024
2. gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation;IEEE Computer Architecture Letters;2024-01
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