T-CAT: Dynamic Cache Allocation for Tiered Memory Systems With Memory Interleaving

Author:

Lee Hwanjun1ORCID,Lee Seunghak1ORCID,Jung Yeji1ORCID,Kim Daehoon1ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Science, DGIST, Daegu, South Korea

Funder

Samsung Electronics Co., Ltd

National Research Foundation of Korea

Institute of Information and communications Technology Planning and Evaluation

Korea government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Hardware and Architecture

Reference13 articles.

1. The gap benchmark suite;beamer,2015

2. SPEC CPU2006 benchmark descriptions

3. 3D-Xpath

4. TMO: transparent memory offloading in datacenters

5. Gen-Z: Communication at the speed of memory;krause;IEEE Supercomputing,2017

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1. Application-Attuned Memory Management for Containerized HPC Workflows;2024 IEEE International Parallel and Distributed Processing Symposium (IPDPS);2024-05-27

2. Macro Memory Cell Generator for SKY130 PDK;IEEE Access;2024

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