Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems-Reference-Cited by-同舟云学术

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Published:2016-05 Issue: Volume: Page:
ISSN:
Container-title:2016 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP)
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Author:

Manier Charles-Alix¹,Zoschke Kai¹,Wilke Martin¹,Oppermann Hermann¹,Ruffieux David²,Dalla Piazza Silvio³,Suni Tommi⁴,Dekker James⁴,Allegato Giorgio⁵,Lang Klaus-Dieter⁶

Affiliation:

1. Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin, Germany

2. CSEM SA, rue Jaquet Droz 7, CH-2002 Neuchâtel, Switzerland

3. Micro Crystal AG, Muehlestrasse 14, CH-2540, Grenchen, Switzerland

4. VTT Technical Research Centre of Finland, Tietotie 3, O2044 VTT, Espoo Finland

5. STMicroelectronics, Via C. Olivetti 2, 20864, Agrate Brianza, Italy

6. Technical Univerity of Berlin, 13355, Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7509007/7514818/07514832.pdf?arnumber=7514832

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