A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9177009/9179169/09179357.pdf?arnumber=9179357
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28
2. Enhancing an Asynchronous Circuit Design Flow to Support Complex Digital System Design;2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2022-08-22
3. Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
4. RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones;IEEE Access;2022
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