RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones-Reference-Cited by-同舟云学术

RTL Conversion Method From Pipelined Synchronous RTL Models Into Asynchronous Ones

Author:

Semba Shogo¹^ORCID,Saito Hiroshi²^ORCID

Affiliation:

1. Graduate School of Computer Science and Engineering, The University of Aizu, Aizu-Wakamatsu, Japan

2. School of Computer Science and Engineering, The University of Aizu, Aizu-Wakamatsu, Japan

Funder

Grant-in-Aid for Scientific Research from the Japan Society for the Promotion of Science

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

Reference30 articles.

1. A delay adjustment method for asynchronous circuits with bundled-data implementation considering a latency constraint;yoshimi;Proc SASIMI,2016

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Self-Timed Counter Synthesis;2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM);2024-05-20

2. Desynchronization of a Synchronous Circuit to Synthesize Self-Timed Circuit;2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon);2024-01-29