Author:
Hua Wenmian,Lu Yi-Shan,Pingali Keshav,Manohar Rajit
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements;Journal of Electronic Testing;2024-07-22
2. Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16
3. Opportunistic Mutual Exclusion;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16
4. An Open-Source EDA Flow for Asynchronous Logic;IEEE Design & Test;2021-04
5. Causal Path Identification for Timed and Sequential Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021