Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements

Author:

Iwata HiroshiORCID,Yamasaki Kokoro,Yamaguchi Ken’ichi

Publisher

Springer Science and Business Media LLC

Reference16 articles.

1. Hua W, Lu Y-S, Pingali K, Manohar R (2020) Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. In Proceedings of 26th IEEE International Symposium on Asynchronous Circuits and Systems, pp 11–19

2. Ataei S, Manohar R (2020) Shared-Staticizer for Area-Efficient Asynchronous Circuits. In Proceedings of 26th IEEE International Symposium on Asynchronous Circuits and Systems, pp 94–101

3. Sparso J, Furber S (2002) Principles asynchronous circuit design: A Systems Perspective. Kluwer Academic Publishers

4. Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L, Yakovlev A (1997) Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans Inform Syst E80-D(3):315–325

5. Hulgaard H, Burns SM, Borriello G (1995) Testing asynchronous circuits: A survey. Integr VLSI J 19(3):111–131

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