New Planar Junction Edge Termination Technique Using OPTVLD With a Buried Layer
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/6542005/06525360.pdf?arnumber=6525360
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. The Study of the Main Junction of the VDMOS Termination;2024 Photonics & Electromagnetics Research Symposium (PIERS);2024-04-21
2. A Novel Junction Termination Technique with Excellent Cost-Performance and Extraordinary Anti-Charge-Deviation Ability;2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2023-05-28
3. Failure Analysis and Reliability Improvement of the Corner Region of Variation Lateral Doping Termination;2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2021-09-15
4. Uniform shallow trenches termination design for high‐voltage VDMOS transistor;Electronics Letters;2020-01
5. The Oppositely Doped Islands IGBT Achieving Ultralow Turn Off Loss;IEEE Transactions on Electron Devices;2019-08
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