Self-tested self-synchronization circuit for mesochronous clocking
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/82/19835/00917781.pdf?arnumber=917781
Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip;IEEE Journal of Solid-State Circuits;2024-02
2. A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip;IEEE Journal of Solid-State Circuits;2021-07
4. Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs;2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2017-09
5. Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous;Integration;2016-01
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