Better Circuits for Binary Polynomial Multiplication-Reference-Cited by-同舟云学术

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Better Circuits for Binary Polynomial Multiplication

Published:2019-04-01 Issue:4 Volume:68 Page:624-630
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Find Magnus Gaudal,Peralta Rena^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/8664420/08494787.pdf?arnumber=8494787

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 ^m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

2. HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2ⁿ) Polynomial;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

3. Hardware Addition Over Finite Fields Based On Booth–Karatsuba Algorithm;The Computer Journal;2024-05-08

4. Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-10

5. Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20

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