DC-Model: A New Method for Assisting the Analog Circuit Optimization
Author:
Affiliation:
1. Tsinghua University,School of Integrated Circuits,Beijing,China,100084
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10129281/10129282/10129366.pdf?arnumber=10129366
Reference21 articles.
1. Using ANNs to Size Analog Integrated Circuits
2. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
3. Transfer learning with bayesian optimization-aided sampling for efficient AMS circuit modeling
4. BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks
5. An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble
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1. Multi-Verse Optimization for Two Stage CMOS Operational Amplifier Circuit Design;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20
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