Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring-Reference-Cited by-同舟云学术

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Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring

Published:1988 Issue:8 Volume:35 Page:1257-1263
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kaga T.,Kawamoto Y.,Kure T.,Nakagome Y.,Aoki M.,Sunami H.,Makino T.,Ohki N.,Itoh K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx1/16/152/00002545.pdf?arnumber=2545

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Proposal of Hierarchical Stacked Type Fe-FET NAND/NAND Array and its Application to Logic LSI;IEEJ Transactions on Electronics, Information and Systems;2017

2. The Computational Paradigm of Cellular Automata in Crowd Evacuation;International Journal of Foundations of Computer Science;2015-11

3. A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line;IEEE Transactions on Electron Devices;1990-03

4. Alpha-particle-induced charge transfer between n/sup +/ regions in high-density trench DRAM with isolated p-well structures;IEEE Transactions on Electron Devices;1990

5. New DRAM noise generation under half-V/sub cc/ precharge and its reduction using a transposed amplifier;IEEE Journal of Solid-State Circuits;1989

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