A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line-Reference-Cited by-同舟云学术

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A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line

Published:1990-03 Issue:3 Volume:37 Page:737-743
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kimura S.,Kawamoto Y.,Kure T.,Hasegawa N.,Kisu T.,Etoh J.,Aoki M.,Takeda E.,Sunami H.,Itoh K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx1/16/1800/00047780.pdf?arnumber=47780

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide;Japanese Journal of Applied Physics;2005-04-21

2. High Signal-to-Noise Ratio DRAM Design and Technology;VLSI Memory Chip Design;2001

3. Cosmic and terrestrial single-event radiation effects in dynamic random access memories;IEEE Transactions on Nuclear Science;1996-04

4. 256-Mb DRAM circuit technologies for file applications;IEEE Journal of Solid-State Circuits;1993-11

5. Interfacial structure and dopant redistribution of a tungsten polycide/N+silicon substrate;Journal of Applied Physics;1993-03

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