Low voltage low power CMOS design techniques for deep submicron ICs-Reference-Cited by-同舟云学术

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Low voltage low power CMOS design techniques for deep submicron ICs

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Container-title:VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design
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Author:

Liqiong Wei ,Roy K.,De V.K.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/6598/17617/00812579.pdf?arnumber=812579

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Basic low-voltage high gain amplifier block having multiple-inputs designed using differential FVF;International Journal of Information Technology;2021-02-26

2. Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders;2020 IEEE Nordic Circuits and Systems Conference (NorCAS);2020-10-27

3. A 1.1-V 40-nm CMOS High Linearity Voltage Follower with Improved CM Input Range;2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM);2020-10-23

4. Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods;Japanese Journal of Applied Physics;2016-03-11

5. Recent Trends in Power-Conscious VLSI Design—A Review;Recent Trends in Intelligent and Emerging Systems;2015

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