FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5367680/5377596/05377609.pdf?arnumber=5377609
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. RoDMap: A Reserve-on-Demand Mapper for Spatially-Configured Coarse-Grained Reconfigurable Arrays;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12
2. Efficient Data Streaming for a Tightly-Coupled Coarse-Grained Reconfigurable Array;2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2023-05
3. A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration;IEEE Journal of Solid-State Circuits;2023-01
4. Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning;IEEE Transactions on Parallel and Distributed Systems;2022-05-01
5. An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings;2022 30th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP);2022-03
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