Reduced March SR Algorithm for Deep-Submicron SRAM Testing
Author:
Affiliation:
1. Universiti Malaysia Perlis,Faculty of Electronics Engineering Technology,Arau,Malaysia
2. Universiti Teknikal Malaysia Melaka,Fakulti Teknologi Kejuruteraan, Elektrik dan Elektronik,Melaka,Malaysia
3. Emerald System Design Center,Penang,Malaysia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9862946/9862950/09863178.pdf?arnumber=9863178
Reference16 articles.
1. Architecture for an efficient MBIST using modified march-y algorithms to achieve optimized communication delay and computational speed;nisha;International Journal of Pervasive Computing and Communications,2021
2. An Automation Program for March Algorithm Fault Detection Analysis
3. Siemens;Tessent MemoryBIST User's Manual For Use with Tessent Shell,2020
4. March LR: a test for realistic linked faults
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. SRAM Memory Testing Methods and Analysis;Advances in Systems Analysis, Software Engineering, and High Performance Computing;2023-12-18
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