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Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems

  • Published:2017-05 Issue:5 Volume:25 Page:1714-1724
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Liu CangORCID,Tang Chuan,Xing Zuocheng,Yuan LuechaoORCID,Zhang Yang

Funder

NSF of China

Specialized Research Fund for the Doctoral Program of Higher Education

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Finite Precision Implementation of Recursive Algorithms for Uplink Detection in Cell-Free Networks;2022 IEEE Globecom Workshops (GC Wkshps);2022-12-04

2. A Novel Fully Hardware-Implemented SVD Solver Based on Ultra-Parallel BCV Jacobi Algorithm;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-12

3. Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis;International Journal of Circuit Theory and Applications;2021-10-18

4. A Low-Complexity QR Decomposition with Novel Modified RVD for MIMO Systems;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2021-05-01

5. Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis;2019 32nd IEEE International System-on-Chip Conference (SOCC);2019-09
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