Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input–Output Repeaters-Reference-Cited by-同舟云学术

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Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input–Output Repeaters

Published:2019-07 Issue:7 Volume:27 Page:1537-1547
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kumar Gundu Anil^ORCID,Kursun Volkan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8746725/08667421.pdf?arnumber=8667421

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

2. DEVELOPMENT OF PARAMETERIZED MODEL OF LOGIC ELEMENTS AT CLOCK TREE SYNTHESIS;Proceedings;2024

3. Clock Optimization Techniques;2022 IEEE 5th International Conference on Electronics Technology (ICET);2022-05-13

4. Hybrid Multisource Clock Tree Synthesis;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

5. Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater;Integration;2021-05

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