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Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization

  • Published:2019-08 Issue:8 Volume:27 Page:1933-1946
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Jo KyeongrokORCID,Ahn Seyong,Do Jungho,Song TaejoongORCID,Kim TaewhanORCID,Choi Kyumyung

Funder

Samsung-Seoul National University Collaboration Project

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

2. Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

4. Challenges on Design and Technology Co-Optimization: Design Automation Perspective;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

5. Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
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