Scan Test of Die Logic in 3-D ICs Using TSV Probing

Author:

Noia Brandon,Panth Shreepad,Chakrabarty Krishnendu,Sung Kyu Lim

Funder

National Science Foundation

Semiconductor Research Corporation (SRC)

Graduate Fellowship through the SRC

SRC through the Integrated Circuit and Systems Sciences Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Short Review of Through-Silicon via (TSV) Interconnects: Metrology and Analysis;Applied Sciences;2023-07-18

2. Low-Power Technique for Yield-Enhanced 3D Interconnects;3D Interconnect Architectures for Heterogeneous Technologies;2022

3. A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology;IEEE Transactions on Emerging Topics in Computing;2021-04-01

4. TSV fault contactless testing method based on group delay;International Journal of Electronics;2021-02-16

5. Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-12

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