Author:
Cheng Kuo-Hsing,Hong Kai-Wei,Hsu Chi-Fa,Jiang Bo-Qian
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
5 articles.
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1. Digital Timing Skew Compensation Ciucuit with Adaptive Duty-Cycle Signals;2021 International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB);2021-12-10
2. A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting;IEEE Access;2021
3. A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs;Analog Integrated Circuits and Signal Processing;2017-06-29
4. A high-precision synchronization circuit for clock distribution;Journal of Semiconductors;2015-10
5. A Synchronous Mirror Delay with Duty-Cycle Tunable Technology;2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems;2015-04