Architecture and Design Flow for a Highly Efficient Structured ASIC

Author:

Ho Man-Ho,Ai Yan-Qing,Chau Thomas Chun-Pong,Yuen Steve C. L.,Choy Chiu-Sing,Leong Philip H. W.,Pun Kong-Pang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units;Microprocessors and Microsystems;2023-06

2. A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block;Engineering Research Express;2023-03-01

3. Soft-core embedded FPGA based system on chip;Analog Integrated Circuits and Signal Processing;2021-05-19

4. A Novel Technology Mapper for Complex Universal Gates;Proceedings of the 26th Asia and South Pacific Design Automation Conference;2021-01-18

5. M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-12

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