Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design-Reference-Cited by-同舟云学术

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Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

Published:2018-01 Issue:1 Volume:26 Page:196-200
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ho Weng-Geng^ORCID,Chong Kwen-Siong,Ne Kyaw Zwa Lwin,Gwee Bah-Hwee,Chang Joseph S.

Funder

Agency for Science, Technology and Research, Singapore, through the Public Sector Research Funding

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8240812/08048019.pdf?arnumber=8048019

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Power and Robust Asynchronous SRAM Generated Using AMC Involving SAHB Circuit with QDI Logic;Journal of The Institution of Engineers (India): Series B;2024-03-26

2. Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems;Journal of Electronic Testing;2024-02

3. A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems;IEEE Access;2024

4. Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

5. Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

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