Prelayout interconnect yield prediction

Author:

Christie P.,Jose Pineda de Gyvez

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Overview of Wafer Contamination and Defectivity;Handbook of Silicon Wafer Cleaning Technology;2018

2. Manufacturability Aware Routing in Nanometer VLSI;Foundations and Trends® in Electronic Design Automation;2010

3. Design for manufacturing meets advanced process control: A survey;Journal of Process Control;2008-12

4. Overview of Wafer Contamination and Defectivity;Handbook of Silicon Wafer Cleaning Technology;2008

5. Multi-objective optimization of interconnect geometry;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2003-02

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