The Mesochronous Dual-Clock FIFO Buffer-Reference-Cited by-同舟云学术

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The Mesochronous Dual-Clock FIFO Buffer

Published:2020-01 Issue:1 Volume:28 Page:302-306
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Konstantinou Dimitrios,Psarras Anastasios^ORCID,Nicopoulos Chrysostomos^ORCID,Dimitrakopoulos Giorgos^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8945454/08879706.pdf?arnumber=8879706

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design & Implementation of Novel Asynchronous FIFO;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18

2. PALS: Distributed Gradient Clocking on Chip;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

3. An enhanced reconfigurable dual-clock FIFO for inter-IP data transmission;IEICE Electronics Express;2023-10-25

4. Asynchronous FIFO Design Based on Verilog;Highlights in Science, Engineering and Technology;2023-03-16

5. Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach;Micromachines;2023-02-14

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