Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach

Author:

Li Zhenmin1,Shen Ruimin1,Yi Maoxiang1,Song Yukun1,Wang Xiaolei1,Du Gaoming1ORCID,Huang Zhengfeng1

Affiliation:

1. School of Microelectronics, Hefei University of Technology, Hefei 230009, China

Abstract

Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery. Solving the packet reordering problem is one of the keys to ensure the quality of service (QoS) for NoC. However, traditional packet reordering approaches rely on local reorder buffer, causing on-chip hotspots, which aggravates chip aging and even leads to interconnection failures. In this paper, we present a multistage packet reordering (MPR) approach, which cannot only reduce the transmission latency but also effectively reduces hotspots caused by local reordering. Specifically, we propose multistage reordering buffer (MRB) by reusing channel buffers for implementing MPR. Experimental results show that our proposed approach achieved improved thermal efficiency with reduced hardware resource consumption.

Funder

National Major Scientific Instruments and Equipments Development Project of National Natural Science Foundation of China

Key Cooperation Project of National Natural Science Foundation of China

National Natural Science Foundation of China

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering

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