Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces-Reference-Cited by-同舟云学术

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces

Published:2017-01 Issue:1 Volume:25 Page:21-34
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Paulino Nuno M. C.,Ferreira Joao Canas,Cardoso Joao M. P.

Funder

European Regional Development Fund within the Operational Programme for Competitiveness and Internationalisation–COMPETE 2020 Programme through the Fundação para a Ciência e a Tecnologia

National Funds through the Fundação para a Ciência e a Tecnologia

Fundação para a Ciência e a Tecnologia

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7797597/07506263.pdf?arnumber=7506263

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