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A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

  • Published:2015-11 Issue:11 Volume:23 Page:2671-2675
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chu Myonglae,Kim Byoungho,Lee Byung-Geun

Funder

IC Design Education Center

Space Core Technology Development Program through the Ministry of Education, Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of a 12-bit 30MS/s Pipeline ADC for Image Sensors;2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE);2024-05-24

2. A 3.3V 14-bit 125MS/s pipeline ADC with hybrid 1.8V/3.3V MOSFET technique in 0.18µm CMOS;IEICE Electronics Express;2024-04-10

3. A Multi-Stage Zero-Crossing-Based Amplifier Using Floating-Inverter Amplifier With Background Offset Calibration and Self-Timed Loop;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

4. A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

5. An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04
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