In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code

Author:

Saragada Prasanna Kumar1ORCID,Das Bishnu Prasad1ORCID

Affiliation:

1. Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, Uttarakhand, India

Funder

Science and Engineering Research Board (SERB), Department of Science and Technology, Government of India

Young Faculty Research Fellowship (YFRF) of Visvesvaraya Ph.D. Scheme of Ministry of Electronics and Information Technology, Government of India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference25 articles.

1. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

2. CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays

3. A 42 pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training;gonugondla;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018

4. A 351 TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications;dong;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

5. A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing

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