Area-Efficient In-Memory Computation with Improved Linearity using Voltage-Controlled Delay Cell-based Ring Oscillator
Author:
Affiliation:
1. IIT,Dept. of Electronics and Communication Engineering,Roorkee,India
Funder
Science and Engineering Research Board (SERB)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10467041/10466793/10467059.pdf?arnumber=10467059
Reference19 articles.
1. Deep Neural Networks for Acoustic Modeling in Speech Recognition: The Shared Views of Four Research Groups
2. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices
3. TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks
4. A Reliability-Concerned Compute-in-Memory Behavior Model for Convolutional Neural Network
5. A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices
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