A 12-bit, 1.1-GS/s, Low-Power Flash ADC
Author:
Affiliation:
1. Analog Design Group, Synopsys, Hyderabad, India
2. Department of Electrical and Electronics Engineering (EEE), Birla Institute of Technology and Science, Pilani, Hyderabad, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9726527/09674740.pdf?arnumber=9674740
Reference41 articles.
1. A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
2. A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration
3. A Subranging-Based Nonuniform Sampling ADC With Sampling Event Filtering
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