A 1.38-mW 7-bit 1.7-GS/s Single-Channel Loop-Unrolled SAR ADC in 22-nm FD-SOI With 8.85 fJ/Conv.-Step for GHz Mobile Communication and Radar Systems
Author:
Affiliation:
1. Chair of Circuit Design and Network Theory, Technische Universitat Dresden, Dresden, Germany
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Radiation
Link
http://xplorestaging.ieee.org/ielx7/22/10241248/10066141.pdf?arnumber=10066141
Reference38 articles.
1. Multi-gigabit communication: The ADC bottleneck1;singh;Proc IEEE Int Conf Ultra-Wideband,2009
2. A 39 GHz bandwidth, 2.5 GS/s 7-bit SAR ADC in 22 nm FDSOI CMOS;checca;IEEE MTT-S Int Microw Symp Dig,2021
3. A quad-channel 11-bit 1-GS/s 40-mW collaborative ADC enabling digital beamforming for 5G wireless;aryanfar;IEEE Trans Microw Theory Techn,2019
4. A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS
5. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Power Efficient Quadruple Time- Interleaved 2.5 GS/s 7 bit SAR ADC with Real-Time Data Output;2023 SBMO/IEEE MTT-S International Microwave and Optoelectronics Conference (IMOC);2023-11-05
2. A 0.636 mW 8-bit 90 kS/s SAR ADC in 130 nm CMOS Process;2023 16th International Conference on Advanced Technologies, Systems and Services in Telecommunications (TELSIKS);2023-10-25
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