A 0.636 mW 8-bit 90 kS/s SAR ADC in 130 nm CMOS Process
Author:
Affiliation:
1. University of Novi Sad,Faculty of Technical Sciences,Novi Sad,Serbia,21102
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10315951/10315716/10316029.pdf?arnumber=10316029
Reference16 articles.
1. On matching properties of R-2R ladders in high performance digital-to-analog converters
2. A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
3. A 17 MS/s SAR ADC with energy-efficient switching strategy
4. A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology
5. Design of a Two Stage CMOS Operational Amplifier using 180nm and 90nm Technology;sharma;International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering,2016
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