32 Bit $\times\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler

Author:

Zhang Xiaoxiao,Boussaid Farid,Bermak Amine

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Low Power Single-Phase-Clock Flip Flop;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19

2. A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure;Electronics;2022-08-27

3. Comparative Analysis of Single-Phase-Clocked Low Power Flip-Flops with Transmission-Gate Flip-Flop;Journal of Physics: Conference Series;2022-08-01

4. Algorithm Level Error Detection in Low Voltage Systolic Array;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-02

5. Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-05

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