Low Power Single-Phase-Clock Flip Flop
Author:
Affiliation:
1. BMS College of Engineering,Dept. of ECE,Bangalore,Karnataka,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10169132/10169913/10170553.pdf?arnumber=10170553
Reference11 articles.
1. Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints
2. A 0.4 V 0.5fJ/cycle TSPC flipflop in 65 nm LP CMOS with retention mode controlled by clockgating cells;moreau;Proc IEEE Int Symp Circuits Syst (ISCAS),2019
3. 32 Bit $\times\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
4. Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing
5. Ultra-Low Power QRS Detection and ECG Compression Architecture for IoT Healthcare Devices
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