A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K

Author:

Onishi TakayukiORCID,Sano Takashi,Nishida Yukikuni,Yokohari Kazuya,Nakamura Ken,Nitta Koyo,Kawashima Kimiko,Okamoto Jun,Ono Naoki,Sagata Atsushi,Iwasaki Hiroe,Ikeda Mitsuo,Shimizu Atsushi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fast rough mode decision algorithm and hardware architecture design for AV1 encoder;Journal of Real-Time Image Processing;2024-09-12

2. Parallel prediction methods for display stream compression encoder;IEICE Electronics Express;2024-06-25

3. A Reconfigurable Multiple Transform Selection Architecture for VVC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05

4. A High-Throughput Hardware Design for the AV1 Decoder Intraprediction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

5. A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders;Parallel and Distributed Computing, Applications and Technologies;2023

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