Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling-Reference-Cited by-同舟云学术

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Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

Published:2012-08 Issue:8 Volume:20 Page:1487-1495
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Crupi F.,Alioto M.,Franco J.,Magnone P.,Kaczer B.,Groeseneken G.,Mitard J.,Witters L.,Hoffmann T. Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/6218240/05959243.pdf?arnumber=5959243

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Simulation Study: Process, Device and Circuit Implementation of Tubs in the BOX (TBOX) cSiGe PMOSFET having low Off State Leakage Current;2022 IEEE Delhi Section Conference (DELCON);2022-02-11

2. Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling;Journal of Low Power Electronics and Applications;2016-06-14

3. Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-12

4. Impact of III–V and Ge Devices on Circuit Performance;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-07

5. Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits;IEEE Transactions on Electron Devices;2013-03

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