System-level power-performance tradeoffs for reconfigurable computing-Reference-Cited by-同舟云学术

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System-level power-performance tradeoffs for reconfigurable computing

Published:2006-07 Issue:7 Volume:14 Page:730-739
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Noguera J.,Badia R.M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/34767/01661622.pdf?arnumber=1661622

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reconfigurable TPM Implemented with Ultralow-Power Management in 28nm CMOS Process for IoT SoC Design;Journal of Hardware and Systems Security;2021-01-19

2. Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs;ACM Transactions on Design Automation of Electronic Systems;2010-02

3. Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms;Journal of Signal Processing Systems;2009-03-10

4. A framework for low energy data management in reconfigurable multi-context architectures;Journal of Systems Architecture;2009-02

5. Towards Novel Approaches in Design Automation for FPGA Power Optimization;Lecture Notes in Computer Science;2009

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