Towards Novel Approaches in Design Automation for FPGA Power Optimization
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Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-540-95948-9_42
Reference16 articles.
1. Paulsson, K., Hübner, M., Becker, J.: On-Line Optimization of FPGA Power- Dissipation by Exploiting Run-time Adaption of Communication Primitives. In: SBCCI 2006, Brazil (2006)
2. Paulsson, K., Huebner, M., Becker, J.: Cost - and Power Optimized FPGA Based System Integration: Methodologies and Integration of a Low-Power Capacity- Based Measurement Application on Xilinx FPGA. In: DATE 2008, Munich, Germany (2008)
3. IBM; On-Chip Peripheral Bus, Architecture Specifications (2001)
4. Shang, L., Kaviani, S.A.S., Bathala, K.: Dynamic Power Consumption in Virtex II FPGA Family. In: Proc. of the 2002 ACM/SIGDA 10th Int. Symp. on Field- Programmable Gate Arrays (2002)
5. Ullmann, M., Hübner, M., Grimm, B., Becker, J.: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. In: Proc. of the 11th Reconfigurable Architectures Workshop (RAW/IPDPS) (April 2004)
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