SLECTS: Slew-Driven Clock Tree Synthesis

Author:

Liu Weicheng,Sitik CanORCID,Salman EmreORCID,Taskin BarisORCID,Sundareswaran Savithri,Huang Benjamin

Funder

Semiconductor Research Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Clock Network Design Challenges;2023 IEEE XVI International Scientific and Technical Conference Actual Problems of Electronic Instrument Engineering (APEIE);2023-11-10

2. An Enhanced Clock Tree Synthesis Methodology for Optimizing Power in Physical Design;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15

3. A Charger Ripple Inhibition Strategy for Motor Train Unit Based on Compound Control;2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT);2022-07-01

4. A Clock Tree Synthesis Scheme Based On Flexible H-tree;2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT);2022-07-01

5. Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel Protection;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-06

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